The present invention relates to image processing apparatus and image processing methods for use in an electronic imaging apparatus such as digital camera.
General procedures of image processing in an electronic imaging apparatus such as digital camera using a solid-state imaging device for example of CCD will be summarized below by way of the block diagram of a digital camera shown in FIG. 1. First, imaging signals outputted from CCD imaging device 101 are treated with pre-process processing at a pre-process section 103 and then once stored as image data in SDRAM 104. Subsequently, the image data are read out from SDRAM 104 and sequentially subjected to a plurality of image processing at an image processing section 105 and are stored again into SDRAM 104. Finally, the image data after the image processing stored in SDRAM 104 are displayed on a display section 106 or further subjected for example to JPEG processing to be recorded on a recording medium such as a memory card 107. Denoted by a numeral 102 in FIG. 1 is CPU for controlling each section.
In achieving such processing procedure for image data, the image processing of one frame has conventionally been effected by first dividing the image data of one frame into a number of strips of small block image data (referred to as block line). A method is then used in which transferred data amount is reduced by sequentially processing each of the block lines so that the plurality of image processing can be effected through a small-capacity memory. Such image processing method has been disclosed for example in Japanese Patent Application Laid-Open 2000-312327.
A description will now be given by way of the timing chart of FIG. 2 with respect to operation of each section when image processing is sequentially executed by such division into the strips of small block images. First CPU 102 effects an initialization operation for setting parameters necessary for the image processing at the image processing section 105 to register of the image processing section 105. CPU 102 then cancels a reset of the image processing section 105 and gives DMA start instructions to an input DMA and output DMA of the image processing section 105. One block line is thereby read out from SDRAM 104 through the input DMA to the image processing section 105 and the image processing of the one block line is effected at the image processing section 105. The one block line after the image processing then is stored again into SDRAM 104 through the output DMA.
Upon termination of such processing, a DMA completion interrupt is sent to CPU 102. When CPU 102 is interrupted in this manner, CPU 102 acknowledges termination of the processing of the first block line, applies a reset on the image processing section 105, and sets the parameters for the next block line processing again to register of the image processing section 105. CPU 102 then cancels the reset on the image processing section 105 and gives DMA start instructions. The processing of one frame is thus effected by sequentially performing the procedures where the image processing of the next block line is similarly effected.